This invention relates to programmable logic devices (“PLDs”) or the like, and more particularly to PLD circuitry that facilitates use of the PLD to support any of many different data communication protocols, especially protocols that involve the use of one or more high-speed serial data streams.
High-speed serial data communication is increasingly of interest, e.g., for signaling between various devices in a system such as integrated circuits on a printed circuit board. The speed at which such communication is desired is constantly increasing, and the known standards or protocols for such communication are also proliferating. Examples of some of these standards or protocols are Gigabit Ethernet, XAUI, FC, SRIO, PCI-Express, etc. Currently, data rates in the range of about 6 gigabits per second are being employed; but this is only an example, and faster or slower data rates may also be employed. As an alternative to protocols that are more or less industry standards, some system designers may want to design their own custom protocols.
PLDs are typically intended to be relatively general-purpose devices. As such, it is desirable for a PLD to be able to support as many different communication protocols as is reasonably feasible. This is made more difficult by both of the trends noted above, i.e., increased communication speed and increased number of possible communication protocols. High speed suggests a need for dedicated circuitry. However, increased number of possible protocols suggests that a large amount of dedicated circuitry will be needed (to support the peculiarities of each possible protocol), but that much of that circuitry will be unused and therefore wasted when the PLD is used for only one or at most a few of the possible protocols.